1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device having a multi-bit constitution, in which the output buffer stages are driven by each sequential output of the delay control means. Sequential time-delayed signals are output by the output buffer stage to prevent a rush current from flowing at the beginning of the data output and to eliminate a malfunction in a memory device and associated circuits thereof.
2. Description of the Related Art
In a known semiconductor memory device such as a dynamic RAM having multi-bit output stages constituted by, e.g., 16K.times.4 bits or 8K.times.8 bits, when data is transmitted at the output stage, large capacitive loads in an exterior data bus line are simultaneously charged or discharged immediately after commencing the transmission of the data output. As a result, a large current flows through a line from the positive side power source line to the output terminal or through a line from the output terminal to the ground side power source line during the period in which the output is changed from a low level to a high level, or vice versa. This excessive transient current is likely to cause a fluctuation of the potential at the positive side power source line or at the ground side source line. The fluctuation is due to insufficient capacity of the power source and parasitic resistance of the power source line, and thus causes a malfunction in the semicondutor memory device itself or in its associated circuits.
In particular, the fluctuation of the potential along the ground side power source line is undesirable to avoid malfunctions because this line is usually used as a reference potential line which determines the logic levels of signals. This problem is serious in memory devices of multi-bit type which generates plural output data signals each time in response to address signals for one address.
While the large transient current should be avoided to eliminate the malfunction as stated above, the output buffers contained in the device for generating the data outputs should have sufficient ability of driving external lines for fast read-out operation, resulting in undesirable amount of potential fluctuation along the power source lines particularly when all the data output each time has the same polarity.